Design and characterization of a 10 nm finfet

Authors

  • Kim Ho Yeap Universiti Tunku Abdul Rahman
  • Jun Yi Lee Universiti Tunku Abdul Rahman
  • Wei Long Yeo Universiti Tunku Abdul Rahman
  • Humaira Nisar Universiti Tunku Abdul Rahman
  • Siu Hong Loh Universiti Tunku Abdul Rahman

DOI:

https://doi.org/10.11113/mjfas.v15n4.1234

Keywords:

Drive current, feature size, FinFET, leakage current, saturation current

Abstract

This paper presents the design, characterization, and analysis of a 10 nm silicon negative channel FinFET. To validate the design, we have simulated the output characteristics and transfer characteristics of the transistor. Both of which comply with the standard characteristics of an operational MOSFET. Owing to its efficacy in suppressing short channel effects, the leakage current of the tri-gate transistor is found to be low; whereas, the drive current is sufficiently high. We have also presented the design specifications of the transistor.

Author Biographies

Kim Ho Yeap, Universiti Tunku Abdul Rahman

Centre for Photonics and Advanced Materials Research

Jun Yi Lee, Universiti Tunku Abdul Rahman

Department of Electronic Engineering

Wei Long Yeo, Universiti Tunku Abdul Rahman

Department of Electronic Engineering

Humaira Nisar, Universiti Tunku Abdul Rahman

Department of Electronic Engineering

Siu Hong Loh, Universiti Tunku Abdul Rahman

Centre for Photonics and Advanced Materials Research

References

Ahmad, I., Ho, Y. K., Majlis, B. Y. 2006. Fabrication and characterization of a 0.14 μm CMOS device using ATHENA and ATLAS simulators. International Scientific Journal of Semiconductor Physics, Quantum Electronics, and Optoelectronics, 9: 40-44.

Bhole, M., Kurude, A., Pawar, S. 2013. FinFET–benefits, drawbacks and challenges. International Journal of Engineering, Sciences and Research Technology, 2: 3219-3222.

Frank, D. J., Dennard, R. H., Nowak, E., Solomon, P. M., Taur, Y., Wong, H. -S. P. 2001. Device scaling limits of si MOSFETs and their application dependencies. Proceedings of the IEEE, 89: 259-288.

Ho, Y. K., Meng, M. K., Chun, L. K., Chiong, T. P., Nisar, H., Rizman, Z. I. 2016. Design and Analysis of 15 nm MOSFETs. Journal of Telecommunication, Electronic and Computer Engineering, 8: 1-4.

Shehata, N., Gaber, A. R., Naguib, A., Selmy, A. E., Hassan, H., Shoeer, I., Ahmadien, O., Nabeel, R. 2015. 3d multi-gate transistors: Concept, operation, and fabrication. Journal of Electrical Engineering, 3: 1-14.

Snider, G. S. and Williams, R. S. 2007. CMOS architectures using a field-programmable nanowire interconnect. Nanotechnology, 18: 035204.

Somra, N., Mishra, K., and Sawhney, R. S. 2015. Optimizing current characteristics of 32 nm FinFET by controlling fin width. Communications on Applied Electronics, 2: 1-5.

Sze, S. M. 2002. Semiconductor Devices: Physics and Technology. US: John Wiley and Sons, 2nd ed., 186 – 204.

Yeap, K. H., Liew, J. G., Loh, S. H., Nisar, H., Rizman, Z. I. 2015.

Performance analysis of 22 nm deep submicron NMOS transistors. Proceedings of the 6th Asia Symposium on Quality Electronic Design. 4-5 August. Kuala Lumpur, Malaysia, 123-126.

Yeap, K. H. Nisar, H. 2018. Very Large Scale Integration. Croatia: InTech. 1- 9.

Yu, B., Chang, L., Ahmed, S., Wang, H., Bell, S., Yang, C. –Y., Tabery, C., Ho, C., Xiang, Q., King, T. –J., Bokor, J., Hu, C., Lin, M. –R., Kyser, D. 2002. FinFET scaling to l0 nm gate length. International Electron Devices Meeting. San Francisco. 8-11 December. USA, 251 – 254.

Downloads

Published

25-08-2019